In***eon Technologies : CY7C1361C/CY7C1363C, 9-Mbit (256K × 36/512K × 18) ...
Mar 28, 2019 — The CY7C1361C/CY7C1363C is a 3.3 V, 256K × 36/512K × 18 ... Maximum access delay from clock rise is 6.5 ns (133 MHz version).
Di***ey : CY7C1363C-133AXC Infineon Technologies
Order today, ships today. CY7C1363C-133AXC – SRAM - Synchronous, SDR Memory IC 9Mbit Parallel 133 MHz 6.5 ns 100-TQFP (14x20) from Infineon Technologies.
Mo***r Electronics : CY7C1363C-133AXC Infineon Technologies
Specifications ; Memory Size: 9 Mbit ; Organization: 512 k x 18 ; Access Time: 6.5 ns ; Maximum Clock Frequency: 133 MHz.
Mo***r Electronics : CY7C1363C-133AXCT Infineon Technologies
Specifications ; Organization: 512 k x 18 ; Access Time: 6.5 ns ; Maximum Clock Frequency: 133 MHz ; Interface Type: Parallel.
Al***bout Circuits : CY7C1363C-133AXC Cypress Semiconductor - Datasheet ...
CY7C1363C Series 9 Mb (512 K x 18) 133 MHz 3.3 V Flow-Through SRAM -TQFP-100. SRAM Chip Sync Dual 3.3V 9M-bit 512K x 18 6.5ns 100-Pin TQFP Tray.
Ar*** Electronics : Infineon Technologies AG CY7C1363C-133AXC SRAM Chip
Product Technical Specifications ; Max. Access Time (ns), 6.5 ; Maximum Clock Rate (MHz), 133 ; Process Technology, 90nm, CMOS ; Minimum Operating Supply Voltage (V) ...
Ar*** Electronics : CY7C1363C-133AXC by Infineon Technologies AG
Product Technical Specifications ; Maximum Clock Rate (MHz): 133 Maximum Clock Rate is fundamental rate in cycles per second (measured in hertz). ; Process ...
Oc***art : CY7C1363C-133AXC Infineon | Distributors, Price, ...
CY7C1363C Series 9 Mb (512 K x 18) 133 MHz 3.3 V Flow-Through SRAM -TQFP-100 · SRAM Chip Sync Dual 3.3V 9M-bit 512K x 18 6.5ns 100-Pin TQFP Tray · 8MB(512KX18) ...
AL***TASHEET : CY7C1363C-133AJXI Datasheet(PDF) - Cypress ...
A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. Features • Supports 133 ...