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Designed for 2V to 5.5V VCC operation and supports mixed-mode voltage operation on all ports. ... Utilizes silicon gate CMOS technology to achieve operating ...
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SN74LVC112APWT - Dual Negative-Edge-Triggered J-K Flip-Flop With Clear And Preset in a TSSOP (PW) package with 16 pins.
Te*** Instruments : SN74LVC112A Dual Negative-Edge-Triggered J-K Flip- ...
3 Description. • ESDProtectionExceedsJESD22. This dual negative-edge-triggered J-K flip-flop is designed for 1.65-V to 3.6-V VCC operation.
Di***ey : SN74LVC112APWT - Integrated Circuits (ICs)
SN74LVC112APWT ; Number of Bits per Element. 1 ; Clock Frequency. 150 MHz ; Max Propagation Delay @ V, Max CL. 5.9ns @ 3.3V, 50pF ; Trigger Type. Negative Edge.
AL***TASHEET : SN74LVC112APWT Datasheet(PDF) - Texas Instruments
DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET, SN74LVC112APWT Datasheet, SN74LVC112APWT circuit, SN74LVC112APWT data sheet : TI, ...
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Compatible with Eagle, Altium, Cadence OrCad & Allegro, KiCad, & more. Discover parts from Texas Instruments, Microchip, TE Connectivity, Vishay & more. SnapEDA ...
Ex***ss Technology Group : SN74LVC112APWT - Texas Instruments - Integrated Circuits
Manufacturer: Texas Instruments; Description: IC DUAL F-F W/CLR/PRESET 16TSSOP; Qty In-Stock: click box for stock check; Qty Available: Stock Check; Price:.
Di***ip : ti SN74LVC112A, Dual Negative-edge-triggered J-k Flip-flop
Details, datasheet, quote on part number: SN74LVC112APWT ; Rating, Catalog ; Output Drive (IOL/IOH)(Max)(mA), -24/24 ; Schmitt Trigger, No ; Approx. Price (US$) ...
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